1. Field of the Invention
The present invention relates to a digital signal processor which is suitable for curtailment of the electric power consumption.
2. Prior Art
Some personal computers used in recent years are equipped with sound source boards. These sound source boards are adapted to perform not only reproduction processing of reproducing musical tones based upon musical performance data given in the form of MIDI (Musical Instrument Digital Interface) data or the like, but also coding and decoding processing of converting an analog sound signal given from an external device outside the personal computer into digital sound data and converting such digital sound data into an analog sound signal, using a codec part within the sound source board. The sound source boards are able to further perform various other processings to process the digital sound data thus obtained, such as rate conversion processing of converting the sampling rate of the data, filtering processing, and mixing processing of mixing the data with other digital sound data. The digital sound data obtained by these processings are finally recorded in a storage device such as a hard disk drive within the personal computer (the above-mentioned processings other than the reproduction processing will be hereinafter generally called xe2x80x9crecording processingxe2x80x9d). The reproduction processing and the recording processing are generally carried out by the use of a digital signal processor (hereinafter called xe2x80x9cDSPxe2x80x9d).
Such a DSP is comprised of an operation part (arithmetic device) for carrying out operations of summing products and others, input and output parts as interfaces, and a control part including a ROM (Read Only Memory) storing commands or instructions for controlling the operation part and the input and output parts. Responsive to a clock signal supplied from an external device to the DSP, fixed-length instructions for the reproduction processing and the recording processing are read out from the ROM within the control part, so that various parts of the DSP operate to sequentially execute the readout instructions. The above clock signal is also used as an operating clock for various parts of the DSP.
In the meanwhile, an increase in the electric power consumption of an electric circuit may raise not only a problem of an increased power consumption amount but also an increased cost of the power supply circuit, and therefore, also in personal computers there is a demand for reduced electric power consumption. Particularly, laptop computers and notebook-sized computers, which operate on electric power from a battery, are seriously required to have reduced amounts of power consumption when they are continuously operated for a long time. To this end, in DSPs of the above-mentioned kind, an attempt has been made to curtail the power consumption by allowing supply of the clock signal to the DSP only when it is needed and interrupting the same (or inhibiting the clock signal from being input) when it is not needed, to stop the operation of the DSP.
FIG. 1 is a timing chart showing the operation of an DSP having the above-mentioned power curtailment function. In FIG. 1, the upper row shows kinds of processing performed by the DSP, and the lower row shows a clock signal supplied to the DSP. In FIG. 1, the time period T, which is the sum of time periods ta and tb, corresponds to one sampling period. In other words, all the instructions stored in the ROM should be executed within the time period T. In the illustrated example, the DSP causes the clock signal to start to be supplied to the DSP, executes all the processings according to the fixed-length instructions within the time period ta, and stops the clock signal from being supplied upon completion of the execution of all the fixed-length instructions. Since the time period tb is obtained by subtracting the time period ta from the time period T, the DSP is inoperative to reduce the power consumption during the time period tb while it is operative consuming the electric power during the time period ta. During the time period ta, a series of processings comprising the reproduction processing and the recording processing are carried out according to the fixed-length instructions. On this occasion, the DSP reads out the predetermined fixed-length instructions from the ROM and sequentially executes reproduction processing, recording processing, reproduction processing, and recording processing in the order mentioned.
Although in the illustrated example the fixed-length instructions contain programs corresponding respectively to the reproduction processing and the recording processing, in actuality all the processings are not always executed for every piece of sampling data. That is, although the fixed-length instructions contain a plurality of processing programs so as to provide the maximum possible effects, in actuality a case where all the processing programs are not executed occurs more frequently than a case where all the processing programs are executed. As the former case, for example, if only the reproduction processing, which appears twice in FIG. 1 is to be executed for a cetain piece of sampling data, the DSP does not perform any processing during the time period t2 corresponding to the recording processing appearing twice in FIG. 1, but the clock signal continues to be supplied to the DSP so that the DSP continues operating even during the time period t2, resulting in wasteful consumption of the electric power.
It is therefore an object of the present invention to provide a digital signal processor which is capable of controlling (reducing or restraining) the electric power consumption in a fine manner according to the contents of processing to be executed.
To attain the above object, the present invention provides a digital signal processor comprising an arithmetic device that performs arithmetic operations according to operation instructions, a storage device that stores plural sets of the operation instructions and control instructions corresponding to respective ones of the operation instructions, for discriminating the respective ones of the operation instructions, and a control device that is disposed to receive an externally supplied control signal, the control device reading out the operation instructions and the control instructions corresponding to the respective ones of said operation instructions and controlling operation of the arithmetic device based upon the control signal and the control instructions read out.
To attain the above object, the present invention also provides a digital signal processor comprising an arithmetic device that performs arithmetic operations according to operation instructions, a storage device that stores plural sets of the operation instructions and control instructions corresponding to respective ones of the operation instructions and indicative of kinds of processings to be executed according to the respective ones of the operation instructions, and a control device that is disposed to receive an externally supplied control signal indicative of kinds of processings to be executed by the digital signal processor, the control device reading out the operation instructions and the control instructions corresponding to the respective ones of the operation instructions and rendering the arithmetic device inoperative when a kind of processing indicated by the control signal and a kind of processing indicated by each of the control instructions read out do not coincide with each other.
To attain the above object, the present invention further provides a digital signal processor for executing a plurality of processings in a time-sharing manner, comprising an arithmetic device that performs arithmetic operations according to operation instructions, a storage device that stores plural sets of the operation instructions and control instructions corresponding to respective ones of the operation instructions and indicative of kinds of the plurality of processings to be executed according to the respective ones of the operation instructions, and a control device that is disposed to receive an externally supplied control signal indicative of kinds of the plurality of processings to be executed by the digital signal processor, the control device reading out the operation instructions and the control instructions corresponding to the respective ones of the operation instructions and rendering the arithmetic device inoperative when a kind of processing indicated by the control signal and a kind of processing indicated by each of the control instructions read out do not coincide with each other.
Preferably, the control device renders the arithmetic device inoperative by inhibiting one of the operation instructions, to which the each of the control instructions read out corresponds, from being supplied to the arithmetic device.
Alternatively, the control device renders the arithmetic device inoperative by inhibiting a clock signal, on which the arithmetic device operates, from being supplied to the arithmetic device.
The present invention can be applied even to a digital signal processor, wherein the arithmetic device comprises CMOS transistors which have very low electric power consumption, so as to further reduce the electric power consumption.
Advantageously, the storage device comprises a non-volatile memory, such as a ROM.
Alternatively, the storage device may comprise a volatile memory such as a RAM. In this case, it may be so arranged that the plural sets of operation instructions and control instructions are transferred to the non-volatile memory from an external hard disk or the like, upon the start of operation of the digital signal processor.
The above and other objects, features, and advantages of the invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.